Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
8.10 Test Access to Transmit Swith Element RAM (TS_RAM)
Address: 180000h (600000h byte)
Index: 1h
Number of entries: 192 (12 cells)
Type: Read/Write during SW_RESET (refer to “SW_RESET” on page 101).
Format: Refer to the following table.
Field (Bits)
Description
TX_SWITCH_ELEMENT_RAM Test access to the TS_RAM.
(31:0)
9 EXTERNAL RAM MEMORY MAP
9.1 External RAM Summary
The external RAM contains:
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•
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Address Lookup RAM (AL_RAM)
Channel RAM (CH_RAM)
Channel Head/Tail and Statistics RAM (AB_RAM)
Receive Cell Buffer SDRAM/SGRAM (RX_DRAM)
Transmit Cell Buffers SDRAM/SGRAM (TX_DRAM)
The following is a memory map of the external RAM, including addresses for the possible
SRAM_CONFIG values.
Byte
Address
Long Address
Name
Description
800000h
200000h
Address Lookup RAM (AL_RAM)
Contains the address lookup tables, linked
lists, and multicast pointer FIFOs.
1000000h
1800000h
400000h
600000h
Channel RAM (CH_RAM)
AB_RAM
Contains the channel tables.
Contains the head and tail pointers for the
receive channel queues.
2000000h
3000000h
800000h
C00000h
Receive Cell Buffer SDRAM/SGRAM
(RX_DRAM_REGISTER)
Receive buffer SDRAM/SGRAM.
Transmit Cell Buffers SDRAM/SGRAM
(TX_DRAM_REGISTER)
Transmit buffer SDRAM/SGRAM.
NOTES:
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All ports marked as “Reserved” must be initialized to 0 at initial setup. Software modifications to these
locations after setup may cause incorrect operation.
All read/write port bits marked “Not used” must be written with the value 0 to maintain software com-
patibility with future versions.
All read-only port bits marked “Not used” are driven with a 0 and should be masked off by the software
to maintain compatibility with future versions.
173
PMC [ PMC-SIERRA, INC ]
