Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.2.4 RX_NEXT_CELL (Internal Structure)
Base address (refer to “AL_RAM_CONFIG” on page 105):
If AL_RAM_CONFIG = 0h, the base address is 20E000h (838000h byte).
If AL_RAM_CONFIG = 1h, the base address is 21C000h (870000h byte).
If AL_RAM_CONFIG = 2h, the base address is 230000h (8C0000h byte).
If AL_RAM_CONFIG = 3h, the base address is 270000h (9C0000h byte).
Entry number:
If AL_RAM_CONFIG = 0h, the entry number is 8K.
If AL_RAM_CONFIG = 1h, the entry number is 16K.
If AL_RAM_CONFIG = 2h, the entry number is 64K.
If AL_RAM_CONFIG = 3h, the entry number is 64K.
Type: Read/Write – Do not write while SW_RESET (refer to “SW_RESET” on
page 101) is deasserted.
Format: Refer to the following table.
Field (Bits)
Description
RAM is not present in these bit locations.
Not present
(31:16)
RX_NEXT_CELL
(15:0)
Index to the next cell in the receive per-channel linked list. Initialize in an incrementing
pattern starting with 1h in the first location.
179
PMC [ PMC-SIERRA, INC ]
