Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.2.5 Transmit Cell Buffer Control Block (Internal Structure)
Base address (refer to “AL_RAM_CONFIG” on page 105):
If AL_RAM_CONFIG = 0h, the base address is 20C000h (830000h byte).
If AL_RAM_CONFIG = 1h, the base address is 218000h (860000h byte).
If AL_RAM_CONFIG = 2h, the base address is 228000h (8A0000h byte).
If AL_RAM_CONFIG = 3h, the base address is 260000h (980000h byte).
Index: 1h
Entry number:
If AL_RAM_CONFIG = 0h, the entry number is 8K.
If AL_RAM_CONFIG = 1h, the entry number is 16K.
If AL_RAM_CONFIG = 2h, the entry number is 32K.
If AL_RAM_CONFIG = 3h, the entry number is 64K.
Read/Write – Do not write while SW_RESET (refer to “SW_RESET” on page 101) is
deasserted.
If the Arriving Cell is Unicast
Field (Bits)
Description
RAM is not present in these bit locations.
Not present
(31:16)
TX_NEXT_CELL
(15:0)
Index to the next cell in the transmit per-SCQ linked list. Initialize in an incrementing
pattern starting with 1h in the first location.
If Arriving Cell is Multicast
Field (Bits)
Description
Not Present
(31:16)
RAM is not present in these bit locations.
TX_MC_ENQ_PEND
(15)
1
0
The background processor is still queuing cells.
The background processor has finished queuing this cell.
Not used
(14)
Write with a 0 to maintain future software compatibility.
Count of times this cell has been enqueued.
TX_MC_COUNT
(13:0)
180
PMC [ PMC-SIERRA, INC ]
