Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
7.2.9 CONDITION_LATCH_BITS
Each interrupt has a latch bit indicating there has been a failure detected since the last time that
the latch word was read.
Address: 9h (24h byte)
Type: Read-only – Cleared on Read.
Reset Value: All bits reset to 0, unless specified.
Format: Refer to the following table.
Field (Bits)
Description
ACK_FAIL_LATCH
(31:28)
Bit 31 corresponds to port 3, bit 30 corresponds to port 2, bit 29 corresponds to port
1 and bit 28 corresponds to port 0 as follows:
1
No ACK, MNACK, or ONACK was received on the same cell time that
a unicast cell was sent.
0
Normal operation.
Refer to section 3 “Fault Tolerance” starting on page 44 for more information.
UT_SOC_FAIL_LATCH
(27)
1
0
Failure was detected on the RATM_SOC signal.
Normal operation.
UT_CLK_FAIL_LATCH
(26)
1
0
Failure was detected on the UTOPIA clock (ATM_CLK).
Normal operation.
SF_CLK_FAIL_LATCH
(25)
1
0
Failure was detected on the switch fabric clock (SE_CLK).
Normal operation.
RX_UTOP_HEC_FAIL_LATCH
(24)
1
0
The HEC of the receive UTOPIA interface was bad at least once since
this latch was read.
The HEC of the receive UTOPIA interface was good every time it was
measured since this latch was read.
RX_DRAM_PARITY_FAIL_LATCH
(23)
1
0
The parity of the RX_DRAM was bad at least once since this latch was
read.
The parity of the RX_DRAM was good every time it was measured
since this latch was read.
TX_DRAM_PARITY_FAIL_LATCH
(22)
1
0
The parity of the TX_DRAM was bad at least once since this latch was
read.
The parity of the TX_DRAM was good every time it was measured
since this latch was read.
AL_RAM_PARITY_FAIL_LATCH
(21)
1
0
The parity of the AL_RAM was bad at least once since this latch was
read.
The parity of the AL_RAM was good every time it was measured since
this latch was read.
CH_RAM_PARITY_FAIL_LATCH
(20)
1
0
The parity of the CH_RAM was bad at least once since this latch was
read.
The parity of the CH_RAM was good every time it was measured since
this latch was read.
TX_PARITY_FAIL_LATCH
(19:16)
Bit 19 corresponds to port 3, bit 18 corresponds to port 2, bit 17 corresponds to port
1 and bit 16 corresponds to port 0 as follows:
1
The transmit parity calculated over the first 12 nibbles of the cell header
coming into the QRT on SE_D_IN#(3:0) was bad at least once since
this latch was read.
0
The transmit parity was good in every cell since this latch was read.
113
PMC [ PMC-SIERRA, INC ]
