Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
6.5 Processor Interface Timing
A microprocessor cycle starts when the chip select (/CS) and command (/ADS) are asserted. Dur-
ing read cycles, the device asserts /READY to indicate that data on the data bus is valid and dur-
ing write cycles the chip asserts /READY to indicate that the write has finished and data from the
bus can be removed. The microprocessor can terminate the current cycle at any time. As shown in
Figure 63, the device stops driving the bus and deasserts all control lines when the cycle termi-
nates. The current cycle terminates when the device select is deasserted or both read and write are
deasserted. A new cycle can start once the /READY has been deasserted. If the cycle was termi-
nated prematurely before the /READY was asserted, then a new microprocessor cycle can start
after one clock cycle.
MICROPROCESSOR READ CYCLE
......
......
......
......
......
......
......
......
Tcyc
PCLK
/CS
Tcssu
Tcsh
Tradsh
Tradsu
/ADS
Taddrh
Taddrsu
ADDR
Tdath
ADDRDATA(31:0)
DATA
Twesu
Tweh
W_/RD
/INTR
Trclkq
Trclkq
/READY
Figure 63. Microprocessor Read Timing
Symbol
Tcyc
Parameter
Signals
Min
Max
50
Unit
Processor clock frequency
Input address setup time
Input address hold time
Address strobe setup time
Address strobe hold time
Chip select setup time
Chip select hold time
PCLK
12.5
MHz
ns
Taddrsu
Taddrh
Tradsu
Tradsh
Tcssu
ADDRDATA(31:0)
3
1
3
1
3
1
ADDRDATA(31:0)
ns
/ADS
/ADS
/CS
ns
ns
ns
Tcsh
/CS
ns
93
PMC [ PMC-SIERRA, INC ]
