S/UNI®-JET Data Sheet
Released
Pin Name
Type
Pin
No.
Function
RPOHCLK
Output
W13
The Receive PLCP Overhead Clock (RPOHCLK) is
active when PLCP processing is enabled. The frequency
of this signal depends on the selected PLCP format.
RPOHCLK is nominally a 26.7 kHz clock for a DS1 PLCP
frame, a 768 kHz clock for a DS3 PLCP frame, a 33.7
kHz clock for an E1 based PLCP frame, or a 576 kHz
clock for a G.751 E3 based PLCP frame.
RPOHFP and RPOH are updated on the falling edge of
RPOHCLK.
RSCLK
The Framer Recovered Clock (RSCLK) is valid when the
S/UNI-JET is configured as a DS3, E3, or J2 framer for
non-ATM applications by setting the FRMRONLY bit in
the S/UNI-JET Configuration Register.
RSCLK is the recovered clock and timing reference for
RDATO, RFPO/RMFPO, and ROVRHD.
The Framer Recovered Gapped Clock (RGAPCLK) is
valid when the S/UNI-JET is configured as a DS3, E3, or
J2 framer for non-ATM applications by setting the
FRMRONLY bit in the S/UNI-JET Configuration 1
Register and the RXGAPEN bit in the S/UNI-JET
Configuration 2 Register.
RGAPCLK
RGAPCLK is the recovered clock and timing reference
for RDATO. RGAPCLK is held high for bit positions
which correspond to overhead.
LCD
Output
Y14
The Loss of Cell Delineation (LCD) is an active high
signal which is asserted while the ATM cell processor
has detected a Loss of Cell Delineation defect. The
FRMRONLY bit in the S/UNI-JET Configuration 1
Register must be set to logic zero for LCD to be valid.
The Framer Receive Data (RDATO) is valid when the
S/UNI-JET is configured as a DS3, E3, or J2 framer for
non-ATM applications by setting the FRMRONLY bit in
the S/UNI-JET Configuration 1 Register.
RDATO
RDATO is the received data aligned to RFPO/RMFPO
and ROVRHD. RDATO is updated on the active edge (as
set by the RSCLKR register bit) of RSCLK or RGAPCLK.
FRMSTAT
Output
Input
U1
Framer Status (FRMSTAT) is an active high signal that
can be configured to show when one of the J2, E3, DS3,
or PLCP framers have detected certain conditions. The
FRMSTAT output can be programmed via the
STATSEL[2:0] bits in the S/UNI-JET Configuration 2
Register to indicate: E3/DS3 LOF or J2 extended LOF,
E3/DS3 OOF or J2 LOF, PLCP LOF, PLCP OOF, AIS,
LOS, and DS3 Idle. FRMSTAT should be treated as a
“glitch-free” asynchronous signal.
ATM8
L18
The ATM Interface Bus Width Selection (ATM8) input pin
determines whether the S/UNI-JET works with a 8-bit
wide interface (RDAT[7:0] and TDAT[7:0]) or a 16-bit
wide interface (RDAT[15:0] and TDAT[15:0]).
If ATM8 is set to logic one, then the 8-bit wide interface is
chosen. If ATM8 is set to logic zero, then the 16-bit wide
interface is chosen.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
43
PMC [ PMC-SIERRA, INC ]
