S/UNI®-JET Data Sheet
Released
Pin Name
Type
Pin
No.
Function
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Input
C15
A16
B16
D15
C16
A17
B17
D16
C17
D18
E17
D19
D20
E18
F17
E19
The Transmit Cell Data Bus (TDAT[15:0]) carries the
ATM cell octets that are written to the transmit FIFO.
TDAT[15:0] is sampled on the rising edge of TFCLK and
is considered valid only when TENB is simultaneously
asserted and the S/UNI-JET has been selected via the
TADR[2:0] inputs.
The S/UNI-JET can be configured to operate with an 8-
bit wide or 16-bit wide ATM data interface via the ATM8
input pin. When configured for the 8-bit wide interface,
TDAT[15:8] are not used and should be tied to ground.
TPRTY
Input
G19
The Transmit Bus Parity (TPRTY) signal indicates the
parity of the TDAT[15:0] or TDAT[7:0] bus. If configured
for the 8-bit bus (via the ATM8 input pin), then parity is
calculated over TDAT[7:0]. If configured for the 16-bit
bus, then parity is calculated over TDAT[15:0].
A parity error is indicated by a status bit and a maskable
interrupt. Cells with parity errors are inserted in the
transmit stream, so the TPRTY input may be unused.
Odd or even parity selection is made using the TPTYP
register bit.
TPRTY is sampled on the rising edge of TFCLK and is
considered valid only when TENB is simultaneously
asserted and the S/UNI-JET has been selected via the
TADR[2:0] inputs.
TSOC
TENB
Input
Input
G20
H18
The Transmit Start of Cell (TSOC) signal marks the start
of cell on the TDAT bus. When TSOC is high, the first
word of the cell structure is present on the TDAT bus.
It is not necessary for TSOC to be present for each cell.
An interrupt may be generated if TSOC is high during
any word other than the first word of the cell structure.
TSOC is sampled on the rising edge of TFCLK and is
considered valid only when TENB is simultaneously
asserted and the S/UNI-JET has been selected via the
TADR[2:0] inputs.
The Transmit Multi-PHY Write Enable (TENB) signal is
an active low input which is used along with the
TADR[2:0] inputs to initiate writes to the transmit FIFO.
When sampled low using the rising edge of TFCLK, the
word on the TDAT bus is written into the transmit FIFO
selected by the TADR[2:0] address bus. When sampled
high using the rising edge of TFCLK, no write is
performed, but the TADR[2:0] address is latched to
identify the transmit FIFO to be accessed.
A complete 53-octet cell must be written to the transmit
FIFO before it is inserted into the transmit stream. Idle
cells are inserted when a complete cell is not available.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
44
PMC [ PMC-SIERRA, INC ]
