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PM7347-BI 参数 Datasheet PDF下载

PM7347-BI图片预览
型号: PM7347-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口的J2 / E3 / T3 [SATURN USER NETWORK INTERFACE for J2/E3/T3]
分类和应用: 网络接口
文件页数/大小: 341 页 / 1733 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-JET Data Sheet  
Released  
Pin Name  
Type  
Pin  
No.  
Function  
DTCA  
Output  
J17  
The Direct Access Transmit Cell Available (DTCA) output  
signals indicate when a cell is available in the transmit  
FIFO.  
When high, DTCA indicates that the corresponding  
transmit FIFO is not full and a complete cell may be  
written. DTCA can be configured to indicate either that  
the corresponding transmit FIFO is near full and can  
accept no more than four writes or that the  
corresponding transmit FIFO is full. DTCA will thus  
transition low on the rising edge of TFCLK which  
samples Payload byte 43 (TCALEVEL0=0) or 47  
(TCALEVEL0=1) for the 8-bit interface (ATM8=1), or the  
rising edge of TFCLK which samples Payload word 19  
(TCALEVEL0=0) or 23 (TCALEVEL0=1) for the 16-bit  
interface (ATM8=0).  
To reduce FIFO latency, the FIFO depth at which DTCA  
indicates "full" can be set to one, two, three or four cells.  
Note: Regardless of what fill level DTCA is set to indicate  
"full" at, the transmit cell processor can store four  
complete cells.  
The polarity of DTCA (with respect to the description  
above) is inverted when the TCAINV register bit is set to  
logic one.  
The DTCA outputs can be used to support Utopia Direct  
Access mode.  
RDAT[15]  
RDAT[14]  
RDAT[13]  
RDAT[12]  
RDAT[11]  
RDAT[10]  
RDAT[9]  
RDAT[8]  
RDAT[7]  
RDAT[6]  
RDAT[5]  
RDAT[4]  
RDAT[3]  
RDAT[2]  
RDAT[1]  
RDAT[0]  
Output  
T20  
T19  
R17  
T18  
U20  
U19  
T17  
U18  
V17  
U16  
W17  
Y17  
V16  
U15  
W16  
Y16  
The Receive Cell Data Bus (RDAT[15:0]) bus carries the  
ATM cell octets that are read from the receive ATM FIFO  
selected by RADR[2:0]. RDAT[15:0] is tri-stated when  
RENB is high. RDAT[15:0] is updated on the rising edge  
of RFCLK.  
The S/UNI-JET can be configured to operate with an 8-  
bit wide or 16-bit wide ATM data interface via the ATM8  
input pin. RDAT[15:8] will remain tri-stated if ATM8 is set  
to logic one.  
RDAT[15:0] is tri-stated when either the null-PHY  
address (7H) or an address not matching the address  
space set by PHY_ADR[2:0] is latched from the  
RADR[2:0] inputs when RENB is high.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990267, Issue 3  
46  
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