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PM7347-BI 参数 Datasheet PDF下载

PM7347-BI图片预览
型号: PM7347-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口的J2 / E3 / T3 [SATURN USER NETWORK INTERFACE for J2/E3/T3]
分类和应用: 网络接口
文件页数/大小: 341 页 / 1733 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-JET Data Sheet  
Released  
Pin Name  
Type  
Pin  
No.  
Function  
TPOHFP  
Output  
W14  
The Transmit Path Overhead Frame Position (TPOHFP)  
is valid when the FRMRONLY bit in the S/UNI-JET  
Configuration 1 Register is logic zero. The TPOHFP  
output locates the individual PLCP path overhead bits in  
the transmit overhead data stream, TPOH. TPOHFP is  
logic one while bit 1 (the most significant bit) of the path  
user channel octet (F1) is present in the TPOH stream.  
TPOHFP is updated on the falling edge of TPOHCLK.  
The Framer Transmit Frame Pulse/Multi-frame Pulse  
Reference (TFPO/TMFPO) is valid when the S/UNI-JET  
is configured as a DS3, E3, or J2 framer for non-ATM  
applications by setting the FRMRONLY bit in the S/UNI-  
JET Configuration 1 Register to logic one and the  
TXGAPEN bit in the S/UNI-JET Configuration Register to  
logic zero.  
TFPO  
TFPO pulses high for 1 out of every 85 clock cycles  
when configured for DS3, giving a free-running mark for  
all overhead bits in the frame. TFPO pulses high for 1 out  
of every 1536 clock cycles when configured for G.751  
E3, giving a free-running reference G.751 indication.  
TFPO pulses high for 1 out of every 4296 clock cycles  
when configured for G.832 E3, giving a free-running  
reference G.832 frame indication. TFPO pulses high for  
1 out of every 789 clock cycles when configured for J2,  
giving a free-running reference frame indication.  
TMFPO pulses high for 1 out of every 4760 clock cycles  
when configured for DS3, giving a free-running reference  
M-frame indication. TMFPO pulses high for 1 out of  
every 3156 clock cycles when configured for J2, giving a  
free-running reference multi-frame indication. TMFPO  
behaves the same as TFPO for E3 applications.  
TMFPO  
TFPO and TMFPO are updated on the rising edge of  
TICLK or RCLK if loop-timed.  
TGAPCLK  
The Framer Gapped Transmit Clock (TGAPCLK) is valid  
when the S/UNI-JET is configured as a DS3, E3, or J2  
framer for non-ATM applications by setting the  
FRMRONLY bit in the S/UNI-JET Configuration 1  
Register and the TXGAPEN bit in the S/UNI-JET  
Configuration 2 Register.  
TGAPCLK is derived from the transmit reference clock  
TICLK or from the receive clock if loop-timed. The  
overhead bit (gapped) positions are generated internal to  
the device. TGAPCLK is held high during the overhead  
bit positions. This clock is useful for interfacing to devices  
which source payload data only.  
TGAPCLK is used to sample TDATI.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990267, Issue 3  
39  
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