S/UNI®-JET Data Sheet
Released
Figure 71 Framer Mode J2 Receive Output Stream
RSCLK
TS97
TS97
3
TS97
TS96
8
TS97
TS97
TS97
TS1
TS97
TS97
TS97
8
RDATO
1
1
0
1
2
e1
0
m1
6
7
8
1
6
7
RFPO/RMFPO
ROVRHD
Figure 72 Framer Mode J2 Receive Output Stream with RGAPCLK
RGAPCLK
TS96
TS96
TS96
TS96
TS1
TS96
TS90
TS90
TS90
8
RDATO
8
6
7
1
6
7
8
8
The Framer Mode J2 Receive Output Stream diagrams (Figure 71 and Figure 72) show the format
of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the
FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set. Figure 71 shows the data
streams when the S/UNI-JET is configured for the J2 receive format. If the RXMFPO register bit
is a logic zero, RFPO is valid and will pulse high for one RSCLK cycle once each J2 frame with
alignment to the first frame alignment bit on the RDATO data stream (as shown in Figure 71). If
the RXMFPO register bit is a logic one, RMFPO is valid and will pulse high once each J2 multi-
frame aligned to the first frame alignment bit on the RDATO data output stream. ROVRHD will
be high for every overhead bit position on the RDATO data stream. The RGAPCLK output is
available in place of RSCLK when the RXGAPEN bit in the S/UNI-JET Configuration 2 Register
is set to logic one. RGAPCLK remains high during the overhead bit positions as shown in Figure
72.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
316
PMC [ PMC-SIERRA, INC ]
