S/UNI®-JET Data Sheet
Released
Figure 60 Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK
INFO 1
INFO 2
INFO 82
INFO 83
INFO 84
INFO 82
INFO 83
INFO 84
INFO 84
INFO 83
INFO 84
INFO 1
INFO 2
INFO 3
INFO 82
RDATO
The Framer Mode DS3 Receive Output Stream diagrams (Figure 59 and Figure 60) show the
format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when
the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set. Figure 59 shows the data
streams when the S/UNI-JET is configured for the DS3 receive format. If the RXMFPO and
8KREFO register bits are logic zero, RFPO is valid and will pulse high for one RSCLK cycle on
first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register
bit is a logic one (as shown in Figure 59) and the 8KREFO register bit is logic zero, RMFPO is
valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high
for every overhead bit position on the RDATO data stream. As shown in Figure 60 the
RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-JET
Configuration 2 Register is set to logic one. RGAPCLK remains high during the overhead bit
positions and RDATO does not change.
Figure 61 Framer Mode G.751 E3 Transmit Input Stream
TICLK
TDATI
bit 1529 bit 1530 bit 1531 bit 1532 bit 1533 bit 1534 bit 1535
bit 1536
bit13
1
1
1
1
0
1
0
0
0
0
RAI Nat
TFPI/TMFPI
TFPO/TMFPO
Figure 62 Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK
TICLK
TGAPCLK
bit 1529 bit 1530 bit 1531 bit 1532 bit 1533 bit 1534 bit 1535 bit 1536
bit13
bit14
TDATI
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
312
PMC [ PMC-SIERRA, INC ]
