S/UNI®-JET Data Sheet
Released
The Framer Mode G.832 E3 Receive Output Stream diagrams (Figure 67 and Figure 68) show the
format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when
the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set. Figure 67 shows the data
streams when the S/UNI-JET is configured for the E3 G.832 receive format. RFPO or RMFPO
pulses high for one RSCLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3
output data stream on RDATO. ROVRHD will be high for every overhead bit position on the
RDATO data stream. The RGAPCLK output is available in place of RSCLK when the
RXGAPEN bit in the S/UNI-JET Configuration 2 Register is set to logic one. RGAPCLK
remains high during the overhead bit positions as shown in Figure 68.
Figure 69 Framer Mode J2 Transmit Input Stream
TICLK
TS98
TS98
TS98
TS98
TS98
TS98
TS98
TSN
TSN
TSN
8
TDATI
6
7
8
6
7
8
8
6
7
e1
1
1
0
x1
x2
x3
TFPI/TMFPI
TFPO/TMFPO
Figure 70 Framer Mode J2 Transmit Input Stream With TGAPCLK
TICLK
TGAPCLK
TS98
TS98
TS1
TS98
TS98
TS1
TS98
TS1
TSN
TSN
TSN
8
TDATI
7
8
1
7
8
1
8
1
6
7
The Framer Mode J2 Transmit Input Stream diagrams (Figure 69 and Figure 70) show the
expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO
(and TGAPCLK) when the FRMRONLY bit in the S/UNI-JET Configuration 1 Register is set,
and the S/UNI-JET is configured for the J2 transmit format. If the TXMFPI register bit is logic
zero, then TFPI is valid (as shown in Figure 69). The S/UNI-JET will expect TFPI to pulse once
every J2 frame with alignment to the first frame alignment bit on TDATI. If the TXMFPI register
bit is logic one, then TMFPI is valid. The S/UNI-JET will expect TMFPI to pulse once every J2
multi-frame with alignment to the first frame alignment bit on TDATI. If the TXMFPO register
bit is logic zero, then TFPO is valid. The S/UNI-JET will pulse TFPO once every 789 TICLK
cycles, providing upstream equipment with a reference frame pulse. If the TXMFPO register bit
is logic one, then TMFPO is valid and the S/UNI-JET will pulse TMFPO once every 3156
TICLK cycles, providing upstream equipment with a reference multi-frame pulse. The alignment
of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and
TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the
TXGAPEN bit in the S/UNI-JET Configuration 2 Register is set to logic one, as in Figure 70.
TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge
of TGAPCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
315
PMC [ PMC-SIERRA, INC ]
