S/UNI®-JET Data Sheet
Released
Figure 17 16-bit Wide, 27-byte Word Structure
Bit 15 Bit 8 Bit 7
Bit 0
W ord 1
W ord 2
W ord 3
W ord 4
W ord 5
W ord 6
H1
H2
H3
H4
HCS
H5
STATUS/CONTROL
PAYLOAD1
PAYLOAD3
PAYLOAD5
PAYLOAD2
PAYLOAD4
PAYLOAD6
W ord 27
PAYLOAD47
PAYLOAD48
The 16-bit SCI-PHYTM compliant data structure is selected when the ATM8 input is tied low. Bit
15 of each word is the most significant bit, which corresponds to the first bit transmitted or
received. Selection between the 26-byte and 27-byte word structure is done with the DS27_53
register bit in the S/UNI-JET Configuration 1 Register. The 26-byte word structure is chosen
when DS27_53 is set to logic zero. The 27-byte word structure is chosen when DS27_53 is set to
logic one. The start of cell indication input and output (TSOC and RSOC) are coincident with
Word 1 (containing the first two header octets). The HCS octet is only passed through the 27-byte
word structure. Word 3 of this structure contains the HCS octet in bits 15 to 8.
In the receive direction with the 27-byte word structure, the lower 8 bits of Word 3 contain the
HCS status octet. An all-zeros pattern in these 8 bits indicates that the associated header is error
free. An all-ones pattern indicates that the header contains an uncorrectable error. (If the
HCSPASS bit in the RXCP-50 Configuration 2 Register is set to logic zero, the all-ones pattern
will never be passed in this structure.) An alternating ones and zeros pattern (xxAA) indicates that
the header contained a correctable error. In this case the header passed through the structure is the
"corrected" header.
In the transmit direction, with the 27-byte word structure, the HCSB bit in the TXCP-50
Configuration 1 Register determines whether the HCS is calculated internally or is inserted
directly from the upper 8 bits of Word 3. The lower 8 bits of Word 3 contain the HCS control
octet. The HCS control octet is an error mask that allows the insertion of one or more errors in the
HCS octet. A logic one in a given bit position causes the inversion of the corresponding HCS bit
position. (For example a logic one in bit 7 causes the most significant bit of the HCS to be
inverted.)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
274
PMC [ PMC-SIERRA, INC ]
