S/UNI®-JET Data Sheet
Released
Figure 15 J2 Frame Structure
125 uS
777-
784
761-
768
769-
776
752-
760
1-8
9-16 17-24 25-32
785
786
787
788
789
Bit #
Frame 1 TS1 TS2 TS3 TS4
Frame 2 TS1 TS2 TS3 TS4
Frame 3 TS1 TS2 TS3 TS4
Frame 4 TS1 TS2 TS3 TS4
TS95 TS96 TS97 TS98
TS95 TS96 TS97 TS98
1
1
1
0
0
1
0
0
m
0
TS95 TS96 TS97 TS98 x1
TS95 TS96 TS97 TS98 e1
x2
e2
x3
e3
a
m
e5
e4
96 Octets of byte inter-
leaved payload
The J2 framer decodes a unipolar or B8ZS encoded signal and frames to the resulting 6,312
Kbit/s J2 bit stream. Once in frame, the J2 framer provides indications of frame and multiframe
boundaries and marks overhead bits, x-bits, m-bits and reserved channels (TS97 and TS98).
Indications of LOS, bipolar violations, excessive zeroes, change of frame alignment, framing
errors, and CRC errors are provided and accumulated in internal counters.
The J2 transmitter inserts the overhead bits into a J2 bit stream and produces a B8ZS-encoded
signal. The J2 transmitter adheres to the framing format specified in G.704 and NTT Technical
Reference for High Speed Digital Leased Circuit Services.
The processing of the overhead bits in the J2 frame is described in Table 41. In the transmit
direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data using
the TOH, TOHINS, TOHFP, and TOHCLK signals. In the receive direction, the overhead bits are
brought out serially on the ROH data stream.
Table 41 J2 Frame Overhead Operation
Control
TS1-TS96:
Byte Interleaved Payload
TS97-TS98:
Signaling channels
Transmit Operation
Receive Operation
Inserts the ATM cells into
Extracts the ATM cell octet payload and
TS1 to TS96 octets.
performs cell delineation.
Inserts the signaling bytes
from either register bits or
from the TOH and TOHINS
inputs. These bits can be
optionally inserted via TDATI
input when in framer only
mode.
Extracts signaling bytes on the ROH output.
Frame Alignment Signal
Inserts the frame alignment
Finds J2 frame alignment by searching for the
frame alignment signal.
signal automatically.
M-bits:
4kHz Data Link
Inserts the 4 KHz data link
signal from the internal
Extracts the 4 KHz data link signal for the
internal HDLC controller.
HDLC controller or from the
bit oriented code generator.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
272
PMC [ PMC-SIERRA, INC ]
