S/UNI®-JET Data Sheet
Released
The DS3, E3, and J2 primitives can be accumulated independently of the PLCP and cell-based
primitives. An accumulation interval is initiated by writing to one of the PMON event counter
register addresses. After writing to a PMON count register, a number of RCLK clock periods
(three for J2 mode, 255 for DS3 mode, 500 for G.832 E3 mode, and three for G.751 E3 mode)
must be allowed to elapse to permit the PMON counter values to be properly transferred. The
PMON registers may then be read.
PLCP and cell-based primitives can be accumulated independent of the DS3, E3, or J2 primitives.
An accumulation interval is initiated by writing to one of the CPPM event counter register
addresses. After writing to a CPPM count register, a maximum of 67 RCLK clock periods must
be allowed to elapse to permit all the CPPM values to be properly transferred. The CPPM
registers may then be read.
The RXCP-50 and TXCP-50 accumulate cell-based primitives such as received cells, corrected
cell headers, uncorrected cell headers, and transmitted cells. An accumulation interval in each
block is initiated by writing to one of the RXCP-50 or TXCP-50 event counter register addresses.
After writing to a count register, a maximum of 67 RCLK or TICLK clock periods must be
allowed to elapse to permit all the RXCP-50 or TXCP-50 values to be properly transferred. The
RXCP-50 or TXCP-50 count registers may then be read.
Writing to the S/UNI-JET Identification, Master Reset, and Global Monitor Update Registers
causes the PMON, CPPM, RXCP-50, and TXCP-50 performance event counters to latch and a
new accumulation period to start in all four quadrants of the S/UNI-JET. A maximum of 67
RCLK clock periods must be allowed to elapse to permit all the event count registers to be
properly transferred.
13.12 Using the Internal PMDL Transmitter
Note: The access rate to the TDPR Registers is limited by the rate of the internal high-speed
system clock selected by the LINESYSCLK register bit of the S/UNI-JET Miscellaneous Register
(39BH). Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR Clear,
and TDPR Transmit Data Registers should be accessed (with respect to WRB rising edge and
RDB falling edge) at a rate no faster than 1/8 that of the selected TDPR high-speed system clock.
This time is used by the high-speed system clock to sample the event, write the FIFO, and update
the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter
in the line clock) must be considered when determining the procedure used to read and write the
TDPR Registers.
Upon reset of the S/UNI-JET , the TDPR should be disabled by setting the EN bit in the TDPR
Configuration Register to logic zero (default value). An HDLC all-ones idle signal will be sent
while in this state. The TDPR is enabled by setting the EN bit to logic one. The FIFOCLR bit
should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
278
PMC [ PMC-SIERRA, INC ]
