S/UNI®-JET Data Sheet
Released
Control
X-bits:
Spare Bits
Transmit Operation
Inserts the spare bits via
register bits or via TOH and
TOHINS input pins.
Receive Operation
Extracts and presents the x-bits on register
bits. The X-bit states can be debounced and
presented on the ROH output pin. An interrupt
change can be generated to signal a change in
the X-bit state.
A-bit:
Inserts the A-bit via register
bit. The A-bit can be
optionally be asserted when
the J2 framer is in LOF
condition.
Extracts and presents the A-bit on a register
bit. The A-bit state can be debounced and
presented on the ROH output pin. An interrupt
can be generated to signal a change in the A-
bit state.
Remote LOF Indication
E1-E5:
CRC-5 Check Sequence
Automatically calculates and
inserts the CRC-5 check
sequence.
Calculates the CRC-5 check sequence for the
received data stream. Discrepancies with the
received CRC-5 code can be configured to
generate an interrupt. CRC-5 errors are
accumulated in an internal counter.
13.8 S/UNI-JET Cell Data Structure
ATM cells may be passed to and from the S/UNI-JET using a 26-word or 27-word data structure
and a 52-byte or 53-byte word data structure. These data structures are shown in Figure 16,
Figure 17, Figure 18, and Figure 19.
Figure 16 16-bit Wide, 26-byte Word Structure
Bit 15
Bit 8
Bit 7
Bit 0
W ord 1
W ord 2
W ord 3
W ord 4
W ord 5
H1
H2
H3
H4
PAYLOAD1
PAYLOAD3
PAYLOAD5
PAYLOAD2
PAYLOAD4
PAYLOAD6
W ord 26
PAYLOAD47
PAYLOAD48
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
273
PMC [ PMC-SIERRA, INC ]
