S/UNI®-JET Data Sheet
Released
Notes
1. All these register bits must be set to logic zero for the INTB output to be tri-stated. If any one of these
register bits is a logic one, then INTB will be driven to logic zero.
2. To enable these outputs, after setting the desired state, RADR[0] must be set to logic zero, RENB must
be set to logic one, bit 4 of register 09BH must be set to logic one, and RFCLK must transition from
logic zero to logic one.
3. To enable this output, after setting the desired state, RADR[2:0] must be set equal to PHY_ADR[2:0],
RADR[1:0] must be set equal to binary 00, RFCLK must transition from logic zero to logic one.
4. To enable this output, after setting the desired state, TADR[2:0] must be set equal to PHY_ADR[2:0],
TADR[1:0] must be set equal to binary 00, TFCLK must transition from logic zero to logic one.
5. Bit 1 of this register must be logic zero.
12.2 JTAG Test Port
The S/UNI-JET JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP
registers: instruction, bypass, device identification and boundary scan. TAP enables the
following:
•
•
•
•
Reading device input logic levels.
Forcing device output.
Identifying the device.
Bypassing the device scan path.
For more details on the JTAG port, please refer to the Error! Reference source not found.
section.
Table 30 Instruction Register
Length - 3 bits
Instructions
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Selected Register
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
Instruction Codes, IR[2:0]
000
001
010
011
100
101
110
111
Bypass
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
255
PMC [ PMC-SIERRA, INC ]
