S/UNI®-JET Data Sheet
Released
Address
783H
784H
785H
786H-78FH
790H
791H
792H
793H-797H
798H
799H
79AH
79BH
79CH-79FH
7A0H
7A1H
7A2H
7A3H
7A4H-7FFH
Notes
Register
TXCP-50 Test Register 3
TXCP-50 Test Register 4
TXCP-50 Test Register 5
Reserved
TTB Test Register 0
TTB Test Register 1
TTB Test Register 2
Reserved
RBOC Test Register 0
RBOC Test Register 1
XBOC Test Register 1
XBOC Test Register 0
Reserved
PRGD Test Register 0
PRGD Test Register 1
PRGD Test Register 2
PRGD Test Register 3
Reserved
1. Although writing values into unused register bits has no effect, it is recommended, to ensure software
compatibility with future, feature-enhanced versions of the device, to write unused register bits with logic
zero. Reading back unused bits can produce either a logic one or a logic zero; therefore, unused
register bits should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
12.1 Test Mode 0 Details
In test mode 0, the S/UNI-JET allows the logic levels on the device inputs to be read through the
microprocessor interface and allows the device outputs to be forced to either logic level through
the microprocessor interface. The IOTST bit in the S/UNI-JET Master Test Register must be set
to logic one to access the device I/O.
To enable test mode 0, the IOTST bit in the S/UNI-JET Master Test Register is set to logic one
and the device should be left in its default state after reset unless otherwise noted. All Test
Register 1 locations of all blocks must be written with the value 0. Refer to Table 27.
Reading the address locations shown in Table 28 returns the values on the indicated inputs:
Table 28 Test Mode 0 Input Read Address Locations
Addr Bit 7
40CH
Bit 6
Device_ID
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
430H
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
251
PMC [ PMC-SIERRA, INC ]
