S/UNI®-JET Data Sheet
Released
Addr Bit 7
436H
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
444H
465H
RENB3
RADR[2]4
RADR[1]4
RADR[0]4
466H
RFCLK
TFCLK
480H
482H
483H
ATM8
TADR[2]1
PHY_ADR[0]
TENB2
T1 ADR[0]
PHY_ADR[2]
PHY_ADR[1]
TSOC
TADR[1] 1
TPRTY
484H
485H
50CH
50FH
530H
536H
544H
565H
60CH
630H
636H
644H
665H
70CH
730H
736H
744H
765H
TDAT[15]
TDAT[7]
TDAT[14]
TDAT[6]
TDAT[13]
TDAT[5]
TDAT[12] TDAT[11]
TDAT[10] TDAT[9]
TDAT[8]
TDAT[0]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
REF8KI
RADR[0]4
TIOHM
TICLK
TPOH
TPOHINS
RPOS
RCLK
TOHINS
TOH
RNEG
RADR[1]4
Notes
1. Before reading these values, the input must be set to the test state, TENB must be set to logic one, and
TFCLK must transition from logic zero to logic one.
2. Before its value will be captured in the test register, TENB must be set to its test state and TFCLK must
transition from logic zero to logic one.
3. Before its value will be captured in the test register RENB must be set to its test state and RFCLK must
transition from logic zero to logic one.
4. Before reading these values, the input must be set to the test state, RENB must be set to logic one, and
RFCLK must transition from logic zero to logic one.
Writing the address locations shown in Table 29 forces the outputs to the value in the
corresponding bit position. Note: Zeros should be written to all unused test register locations.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
252
PMC [ PMC-SIERRA, INC ]
