S/UNI®-JET Data Sheet
Released
12 Test Features Description
The test mode registers, shown in Table 27, are used for production and board testing.
During production testing, the test mode registers are used to apply test vectors. In this case, the
test mode registers (as opposed to the normal mode registers) are selected when A[10] is high.
During board testing, the digital output pins and the data bus are held in a high-impedance state
by simultaneously asserting (low) the CSB, RDB, and WRB inputs. All of the TSBs for the
S/UNI-JET are placed in test mode 0 so that device inputs may be read and device outputs may be
forced through the microprocessor interface. Refer to the section "Test Mode 0" for details.
Note: The S/UNI-JET supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port
that can be used for board testing. All digital device inputs may be read and all digital device
outputs may be forced through this JTAG test port.
Table 27 Test Mode Register Memory Map
Address
000H-3FFH
400H
708H
709H
Register
Normal Mode Registers
Master Test Register
SPLR Test Register 0
SPLR Test Register 1
SPLR Test Register 2
Reserved
70AH
70BH
70CH
70DH
70EH
70FH
710H
711H
712H-71FH
720H
721H
722H
723H-72FH
730H
731H
732H
733H
734H
735H
736H
SPLT Test Register 0
SPLT Test Register 1
SPLT Test Register 2
SPLT Test Register 3
PMON Test Register 0
PMON Test Register 1
Reserved
CPPM Test Register 0
CPPM Test Register 1
CPPM Test Register 2
Reserved
DS3 FRMR Test Register 0
DS3 FRMR Test Register 1
DS3 FRMR Test Register 2
DS3 FRMR Test Register 3
DS3 TRAN Test Register 0
DS3 TRAN Test Register 1
DS3 TRAN Test Register 2
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
249
PMC [ PMC-SIERRA, INC ]
