S/UNI®-JET Data Sheet
Released
Register 3AEH: PRGD Pattern Detector #3
Bit
Type
R
R
R
R
R
R
R
R
Function
PD[23]
PD[22]
PD[21]
PD[20]
PD[19]
PD[18]
PD[17]
PD[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Register 3AFH: PRGD Pattern Detector #4
Bit
Type
R
R
R
R
R
R
R
R
Function
PD[31]
PD[30]
PD[29]
PD[28]
PD[27]
PD[26]
PD[25]
PD[24]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
PD[31:0]
PD[31:0] contain the pattern detector data. The values contained in these registers are
determined by the PDR[1:0] bits in the control register.
When PDR[1:0] is set to 00 or 01, PD[31:0] contain the pattern receive register. The 32 bits
received immediately before the last accumulation interval are present on PD[31:0}. PD[31]
contains the first of the 32 received bits, PD[0] contains the last of the 32 received bits.
When PDR[1:0] is set to 10, PD[31:0] contain the error counter holding register. The value in
this register represents the number of bit errors that have been accumulated since the last
accumulation interval. Note: Bit errors are not accumulated while the pattern detector is out-
of-sync.
When PDR[1:0] is set to 11, PD[31:0] contain the bit counter holding register. The value in
this register represents the total number of bits that have been received since the last
accumulation interval.
The values of PD[31:0] are updated whenever one of the four PRGD Pattern Detector
Registers is written or when Register 006H, the S/UNI-JET Identification, Master Reset, and
Global Monitor Update Register is written.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
247
PMC [ PMC-SIERRA, INC ]
