S/UNI®-JET Data Sheet
Released
Register 392H: TTB Indirect Address
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RWB
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
A[6:0]
The indirect read address bits (A[6:0]) indexes into the trail trace identifier buffers. When
RRAMACC is set high, decimal addresses 0 to 63 reference the receive capture page while
addresses 64 to 127 reference the receive expected page. The receive capture page contains
the identifier bytes extracted from the receive G.832 E3 stream. The receive expected page
contains the expected trace identifier message downloaded from the microprocessor. When
RRAMACC is set low, decimal addresses 0 to 63 reference the transmit message buffer
which contains the identifier message to be inserted in the TR bytes of the G.832 E3 transmit
stream. In this case A[6] is a don't care (for example, address 0 and address 64 are indexes to
the same location in the buffer). Note: Only the first 16 addresses need to be written with the
trail trace message to be transmitted.
RWB
The access control bit (RWB) selects between an indirect read or write access to the static
page of the trail trace message buffer. Writing to this indirect address register initiates an
external microprocessor access to the static page of the trail trace message buffer. When
RWB is set high, a read access is initiated. The data read is available upon completion of the
access in the TTB Indirect Data Register. When RWB is set low, a write access is initiated.
The data in the TTB Indirect Data Register will be written to the addressed location in the
static page.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
225
PMC [ PMC-SIERRA, INC ]
