S/UNI®-JET Data Sheet
Released
Register 367H: RXCP-50 Idle Cell Header Pattern
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[3]
PTI[2]
PTI[1]
CLP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
1
GFC[3:0]
The GFC[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of
the first octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register.
The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable
dropping of cells matching this pattern. Note: An all-zeros pattern must be present in the VPI
and VCI fields of the idle or unassigned cell.
PTI[2:0]
The PTI[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth
octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register. The
IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of
cells matching this pattern.
CLP
The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet
cell, in conjunction with the Match Header Mask Register. The IDLEPASS bit in the
Configuration 2 Register must be set to logic zero to enable dropping of cells matching this
pattern.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
203
PMC [ PMC-SIERRA, INC ]
