S/UNI®-JET Data Sheet
Released
Register 34CH: J2-TRAN Configuration
Bit
Type
Function
Unused
Reserved
Reserved
Reserved
X3SET
X2SET
X1SET
RLOF
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RLOF
The RLOF bit controls the state of the A-bit. When RLOF is a logic one, the A-bit is also set
to logic one. When RLOF is a logic zero, the A-bit is set to logic zero. The A-bit in the
transmit stream may also be set to logic one if an LOF condition in the J2 FRMR is detected
and the RBLEN bit is logic one in the S/UNI-JET Data Link and FERF/RAI Control Register.
X1SET
The X1SET bit controls the state of the X1 bit (bit 785 in the third frame of a J2 multiframe).
When X1SET is a logic one, the X1 bit is set to logic one. When X1SET is a logic zero, the
X1 bit is set to logic zero.
X2SET
The X2SET bit controls the state of the X2 bit (bit 786 in the third frame of a J2 multiframe).
When X2SET is a logic one, the X2 bit is set to logic one. When X2SET is a logic zero, the
X2 bit is set to logic zero.
X3SET
The X3SET bit controls the state of the X3 bit (bit 787 in the third frame of a J2 multiframe).
When X3SET is a logic one, the X3 bit is set to logic one. When X3SET is a logic zero, the
X3 bit is set to logic zero.
Reserved
The reserved register bits should be set to logic zero for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
171
PMC [ PMC-SIERRA, INC ]
