S/UNI®-JET Data Sheet
Released
Register 348H: J2-FRMR Error/Xbit Interrupt Enable
Bit
Type
R/W
R/W
R/W
R/W
R/W
Function
CRCEE
FRMEE
BPVE
EXZE
XBITE
Unused
XBIT_DEB
XBIT_THR
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
X
0
0
R/W
R/W
CRCEE
When CRCEE is logic one, the J2-FRMR will generate an interrupt if a multiframe fails its
CRC-5 check.
FRMEE
When FRMEE is logic one, the J2-FRMR will generate an interrupt upon the reception of an
errored framing bit.
BPVE
When BPVE is logic one, the J2-FRMR will generate an interrupt upon the reception of a
bipolar violation which is not part of a valid B8ZS code (when UNI is set to logic zero in the
J2-FRMR Configuration Register) or on the reception of a logic one on RLCV (when UNI is
set to logic one).
EXZE
When EXZE is logic one, the J2-FRMR will generate an interrupt upon the reception of a
string of eight-or-more consecutive zeroes. EXZE has no effect when UNI is set to logic one
in the J2-FRMR Configuration Register.
XBITE
When XBITE is logic one, the J2-FRMR will generate an interrupt when any of the x-bits
(X1, X2, X3) change state. Because the XBIT interrupt is generated when the x-bit
indications change, the interrupt is debounced along with them via the XBIT_DEB and
XBIT_THR bits.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
167
PMC [ PMC-SIERRA, INC ]
