S/UNI®-JET Data Sheet
Released
Register 34DH: J2-TRAN Diagnostic
Bit
Type
Function
Unused
Unused
PLDAIS
PHYAIS
DCRC
DLOS
DBPV
DFERR
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
DFERR
The DFERR bit controls the insertion of framing alignment signal errors. When DFERR is set
to logic one, the framing alignment signal is inverted. When DFERR is set to logic zero, the
framing alignment signal is not inverted.
DBPV
The DBPV bit controls the insertion of single bipolar violations. When DBPV bit transitions
from 0 to 1, a violation is generated by masking the first violation pulse of a B8ZS signature.
To generate another violation, this bit must first be written to 0 and then to logic one again.
When DBPV is a logic zero, no violation is generated.
DLOS
When set to logic one, the DLOS bit forces the unipolar and bipolar outputs of the J2 TRAN
to be all zeros. When DLOS is logic zero, the outputs of the J2 TRAN operate normally.
DCRC
When set to logic one, a the CRC-5 check bits (e ) are inverted before transmission. DCRC
1-5
bits even if CDIS of the J2 TRAN Configuration Register is set to logic one.
inverts the e
1-5
PHYAIS
When set to logic one, PHYAIS will cause the J2 TRAN to transmit an all 1's AIS (AIS).
PLDAIS
When set to logic one, PLDAIS will cause the J2 TRAN to insert all-ones in the payload data
bits. When PLDAIS is a logic zero, data is processed normally through the J2 TRAN.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
172
PMC [ PMC-SIERRA, INC ]
