S/UNI®-JET Data Sheet
Released
Register 349H: J2-FRMR Error/Xbit Interrupt Status
Bit
Type
R
R
R
R
R
R
R
R
Function
CRCEI
FRMEI
BPVI
EXZI
XBITI
X3
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
X2
X1
CRCEI
The CRCEI bit is set to logic one if a failed CRC-5 check occurs. CRCEI is cleared when this
register is read.
FRMEI
The FRMEI bit is set to logic one if an errored framing bit occurs. FRMEI is cleared when
this register is read.
BPVI
The BPVI bit is set to logic one if a bipolar violation that is not part of a valid B8ZS code
occurs (when UNI is logic zero in the J2-FRMR Configuration Register) or if a 0 to 1
transition is detected on RLCV (when UNI is logic one). BPVI is cleared when this register is
read.
EXZI
The EXZI bit is set to logic one upon reception of eight-or-more consecutive zeroes. EXZI
remains logic zero while UNI is set to logic one in the J2_FRMR Configuration Register.
EXZI is cleared when this register is read.
XBITI
The XBITI bit is set to logic one if a change in the debounced (if XBIT_DEB is set to logic
one) x-bits (X1, X2, and X3) is detected. XBITI is cleared when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
169
PMC [ PMC-SIERRA, INC ]
