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PM7347-BI 参数 Datasheet PDF下载

PM7347-BI图片预览
型号: PM7347-BI
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口的J2 / E3 / T3 [SATURN USER NETWORK INTERFACE for J2/E3/T3]
分类和应用: 网络接口
文件页数/大小: 341 页 / 1733 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI®-JET Data Sheet  
Released  
Register 350H: RDLC Configuration  
Bit  
Type  
Function  
Unused  
Unused  
Unused  
Reserved  
MEN  
MM  
TR  
EN  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
X
X
X
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
EN  
The EN bit controls the overall operation of the RDLC. When EN is set to logic one, RDLC  
is enabled; when set to logic zero, RDLC is disabled. When RDLC is disabled, the RDLC  
FIFO buffer and interrupts are all cleared. When RDLC is enabled, it will immediately begin  
looking for flags.  
TR  
Setting the terminate reception (TR) bit to logic one forces the RDLC to immediately  
terminate the reception of the current data frame, empty the RDLC FIFO buffer, clear the  
interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate  
reception event in the same manner as it would the toggling of the EN bit from logic one to  
logic zero and back to logic one. Thus, the RDLC state machine will begin searching for  
flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself  
to logic zero after the register write operation is completed and a rising and falling edge  
occurs on the internal datalink clock input. If the RDLC Configuration Register is read after  
this time, the TR bit value returned will be logic zero.  
MEN  
Setting the Match Enable (MEN) bit to logic one enables the detection and storage in the  
RDLC FIFO of only those packets whose first data byte matches either of the bytes written to  
the Primary or Secondary Match Address Registers, or the universal all-ones address. When  
the MEN bit is logic zero, all packets received are written into the RDLC FIFO.  
MM  
Setting the Match Mask (MM) bit to logic one ignores the PA[1:0] bits of the Primary  
Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the  
two least significant bits of the universal all-ones address when performing the address  
comparison.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use  
Document ID: PMC-1990267, Issue 3  
175