S/UNI®-JET Data Sheet
Released
Register 344H: J2-FRMR Configuration
Bit
Type
Function
Unused
UNI
REFRAME
FLOCK
CRC_REFR
SFRME
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LOSTHR[1]
LOSTHR[0]
UNI
When the UNI bit is set to logic zero, the J2-FRMR expects unipolar data on the RDATI
input and LCV indications on the RLCV input. When UNI is logic zero, the J2-FRMR
expects bipolar B8ZS encoded data on the RPOS and RNEG inputs. When UNI is set to logic
one, then the LOS, LOSI, and EXZI indications cannot be used.
REFRAME
Writing the REFRAME bit logic one forces the J2-FRMR to declare LOF, and begin
searching for a new alignment. In order to force another reframe, REFRAME must be written
with logic zero, and then logic one again.
FLOCK
When the FLOCK bit is set to logic one, the J2-FRMR is prevented from declaring LOF and
searching for a new frame alignment due to framing-pattern errors. In this case, the J2-FRMR
will only search for frame alignment when the REFRAME register bit transitions from logic
zero to logic one.
CRC_REFR
When the CRC Reframe Enable bit is set to logic one, an alternate framing algorithm is
enabled, which uses the CRC-5 check to detect framing to a mimic pattern in the payload or
signaling bits. The framer, once it has seen at least one correct framing pattern, begins
looking for correct CRC-5s as well. If it observes three consecutive correct framing patterns,
and two correct CRC-5 sequences, then frame is declared. Otherwise, a reframe is initiated.
When CRC_REFR is set to logic zero, the framing algorithm simply searches for three
consecutive correct framing patterns.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
160
PMC [ PMC-SIERRA, INC ]
