S/UNI®-JET Data Sheet
Released
RLOF_THR
The RLOF Threshold bit determines the number of consecutive a-bits that are required for the
state of RLOF to change. When RLOF_THR is logic zero, RLOF is asserted when the a-bit
has been logic one for three consecutive frames, and de-asserted when the a-bit has been
logic zero for three consecutive frames. When RLOF_THR is logic one, RLOF is asserted
when the a-bit has been logic one for five consecutive frames, and de-asserted when the a-bit
has been logic zero for five consecutive frames. The default setting is that five consecutive a-
bits are required.
PHYAISE
When PHYAISE is logic one, the J2-FRMR will generate an interrupt when a change is
detected in the Physical AIS condition.
PLDAISE
When PLDAISE is logic one, the J2-FRMR will generate an interrupt when a change is
detected in the Payload AIS condition.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
164
PMC [ PMC-SIERRA, INC ]
