S/UNI®-JET Data Sheet
Released
Register 342H: E3 TRAN BIP-8 Error Mask
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MBIP[7]
MBIP[6]
MBIP[5]
MBIP[4]
MBIP[3]
MBIP[2]
MBIP[1]
MBIP[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
MBIP[7:0]
The MBIP[7:0] bits act as an error mask to cause the transmitter to insert up to eight BIP-8
errors. The contents of this register are XORed with the calculated BIP-8 byte and inserted
into the G.832 EM byte of the frame. A logic one in any MBIP bit position causes that bit
position in the EM byte to be inverted. Writing this register with a mask value causes that
mask to be applied only once; if continuous BIP-8 errors are desired, the CPERR bit in the
Status and Diagnostic Options Register can be used.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
157
PMC [ PMC-SIERRA, INC ]
