S/UNI®-JET Data Sheet
Released
FERFI
The FERFI bit is a transition indication. When FERFI is logic one, a change of state of the
Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte),
or when the RAI bit (bit 12 of the frame in G.751) has occurred. When FERFI is logic zero,
no changes in the state of the FERF or RAI bit has occurred since the last time this register
was read.
AISDI
The AISDI bit is a transition indication. When AISDI is logic one, a change in state of the
AISD indication has occurred. When AISDI is logic zero, no changes in the state of the AISD
signal has occurred since the last time this register was read.
PERRI
The PERRI bit is an event indication. When PERRI is logic one, the occurrence of one or
more BIP-8 errors (in G.832 mode) has been detected. When PERRI is logic zero, no
occurrences of BIP-8 errors have occurred since the last time this register was read.
FERRI
The FERRI bit is an event indication. When FERRI is logic one, the occurrence of one or
more framing bit error has been detected. When FERRI is logic zero, no occurrences of
framing bit errors have occurred since the last time this register was read.
The transition/event interrupt indications within this register work independently from the
interrupt enable bits, allowing the microprocessor to poll the register to determine the activity
of the maintenance events. The contents of this register are cleared to logic zero after the
register is read; the INTB output is also cleared to logic one if the interrupt was generated by
any of the Maintenance Event outputs.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
151
PMC [ PMC-SIERRA, INC ]
