S/UNI®-JET Data Sheet
Released
COFAI
The COFAI bit indicates that a change of frame alignment between the previous alignment
and the newly found alignment has occurred. When COFAI is logic one, the last high-to-low
transition on the OOF signal resulted in the new frame alignment differing from the previous
one. The COFAI bit is cleared to logic zero upon the completion of the register read. When
COFAI is logic zero, it indicates that no change in frame alignment has occurred when OOF
went low.
LCVI
The LCVI bit indicates that a LCV has occurred. When LCVI is logic one, a LCV on the
RPOS and RNEG inputs was detected since the last time this register was read. The LCVI bit
is cleared to logic zero upon the completion of the register read. When LCVI is logic zero, it
indicates that no LCV was detected since the last register read. When the UNI bit in the
Framing Options Register is logic one, the LCVI is forced to logic zero.
LOSI
The LOSI bit indicates that a state transition occurred on the LOS status signal. When LOSI
is logic one, a high-to-low or low-to-high transition occurred on the LOS status signal since
the last time this register was read. The LOSI bit is cleared to logic zero upon the completion
of the register read. When LOSI is logic zero, it indicates that no state change has occurred on
LOS since the last time this register was read. When the UNI bit in the Framing Options
Register is logic one, the LOSI is forced to logic zero.
CZDI
The CZDI bit indicates that four consecutive zeros in the HDB3-encoded stream have been
detected. CZDI is asserted to a logic one, whenever the CZD signal is asserted. The CZDI bit
is cleared to a logic zero upon the completion of the register read. When CZDI is logic zero, it
indicates that no occurrences of four consecutive zeros was detected since the last register
read. When the UNI bit in the Framing Options Register is logic one, the CZDI indication is
forced to logic zero.
The interrupt indications within this register work independently from the interrupt enable
bits, allowing the microprocessor to poll the register to determine the state of the framer. The
indication bits (bits 2,3,4,5,6 of this register) are cleared to logic zero after the register is
read; the INTB output is also cleared to logic one if the interrupt was generated by any of
these five events.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
147
PMC [ PMC-SIERRA, INC ]
