S/UNI®-JET Data Sheet
Released
FERFE
The FERFE bit is an interrupt enable. When FERFE is logic one, an interrupt is generated on
the INTB output when the Far End Receive Failure indication bit (bit 1 of the G.832
Maintenance and Adaptation byte), or when the RAI bit (bit 11 of the frame in G.751)
changes state after the selected persistency check is applied. When FERFE is logic zero,
changes in state of the FERF or RAI bit does not cause an interrupt on INTB.
AISDE
The AISDE bit is an interrupt enable. When AISDE is logic one, an interrupt is generated on
the INTB output when the AISD indication changes state. When AISDE is logic zero,
changes in state of the AISD signal does not cause an interrupt on INTB.
PERRE
The PERRE bit is an interrupt enable. When PERRE is logic one, an interrupt is generated on
the INTB output when a BIP-8 error (in G.832 mode) is detected. When PERRE is logic zero,
occurrences of BIP-8 errors do not cause an interrupt on INTB.
FERRE
The FERRE bit is an interrupt enable. When FERRE is logic one, an interrupt is generated on
the INTB output when a framing bit error is detected. When FERRE is logic zero,
occurrences of framing bit errors do not cause an interrupt on INTB.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
149
PMC [ PMC-SIERRA, INC ]
