PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Pin Name
Type
Input
Pin No. Function
RSDATA[7]
RSDATA[6]
RSDATA[5]
RSDATA[4]
RSDATA[3]
RSDATA[2]
RSDATA[1]
RSDATA[0]
V3
Y1
W1
U3
U1
T1
The Receive Serial Data (RSDATA[7:0]) signals
contain the recovered line data for the 8
independently timed links.
For channelized links, RSDATA[n] contains the
24 (T1) or 31 (E1) time-slots that comprise the
channelized link. RSCLK[n] must be gapped
during the T1 framing bit position or the E1 frame
alignment signal (time-slot 0). The S/UNI-IMA-8
uses the location of the gap to determine the
channel alignment on RSDATA[n].
R3
R2
For unchannelized links, RSDATA[n] contains the
ATM cell data. For certain transmission formats,
RSDATA[n] may contain place-holder bits or time-
slots. RSCLK[n] must be externally gapped
during the place-holder positions in the
RSDATA[n] stream.
The RSDATA[7:0] input signals are sampled on
the rising edge of the corresponding RSCLK[7:0]
clock.
CTSCLK
Input
H2
The Common Transmit Serial Clock (CTSCLK)
signal contains a common transmit line clock that
can be used by all of the 8 serial links instead of
the each link’s transmit serial line clock
(TSCLK[n]).
The CTSCLK input signal is nominally a 50%
duty cycle clock of 1.544 MHz for T1 links and
2.048 MHz for E1 links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
