PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Pin Name
Type
Input
Pin No. Function
RSCLK[7]
RSCLK[6]
RSCLK[5]
RSCLK[4]
RSCLK[3]
RSCLK[2]
RSCLK[1]
RSCLK[0]
V1
U2
V4
T3
R1
T4
P3
P2
The Receive Serial Clock (RSCLK[7:0]) signals
contain the recovered line clock for the 8
independently timed links. The RSDATA[7:0]
signals are sampled on the rising edge of the
corresponding RSCLK[7:0] clock.
For channelized T1 or E1 links, RSCLK[n] must
be gapped during the framing bit (for T1
interfaces) or during time-slot 0 (for E1
interfaces) of the RSDATA[n] stream. The S/UNI-
IMA-8 uses the gapping information to determine
the time-slot alignment in the receive stream.
RSCLK[7:0] is nominally a 50% duty cycle clock
of 1.544 MHz for T1 links and 2.048 MHz for E1
links.
For unchannelized links, RSCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e., not part of the ATM cell).
The RSCLK[7:0] input signal is nominally a 50%
duty cycle clock of 1.544 MHz for T1 links and
2.048 MHz for E1 links.
The RSCLK[7:0] may operate at higher rates in
the unchannelized mode. At higher rates, the
amount of lines available is limited See 12.3.1.2
for more details.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
33
PMC [ PMC-SIERRA, INC ]
