PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
9.6 Clk/Data (33 signals)
Pin Name
Type
Pin No. Function
TSCLK[7]
TSCLK[6]
TSCLK[5]
TSCLK[4]
TSCLK[3]
TSCLK[2]
TSCLK[1]
TSCLK[0]
Input
F2
D3
G3
G2
G1
F4
H1
H3
The Transmit Serial Clock (TSCLK[7:0]) signals
contain the transmit clocks for the 8
independently timed links. The TSDATA[7:0]
signals are updated on the falling edge of the
corresponding TSCLK[7:0] clock.
For channelized T1 or E1 links, TSCLK[n] must
be gapped during the framing bit (for T1
interfaces) or during time-slot 0 (for E1
interfaces) of the TSDATA[n] stream. The S/UNI-
IMA-8 uses the gapping information to determine
the time-slot alignment in the transmit stream.
For unchannelized links, TSCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e., not part of the ATM Cell).
The TSCLK[7:0] input signal is nominally a 50%
duty cycle clock of 1.544 MHz for T1 links and
2.048 MHz for E1 links.
The TSCLK[7:0] may operate at higher rates in
the unchannelized mode. At higher rates, the
amount of lines available is limited. See 12.3.1.2
for more details.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
PMC [ PMC-SIERRA, INC ]
