PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x044: SDRAM DIAG Burst RAM Indirect Access
Bit
Type
Function
Default
15
14:5
4:0
R/W
N/A
R/W
BR_BUSY
Unused
BR_ADDR[4:0]
0
N/A
0
Writing to this register triggers an indirect RAM access. See 12.6.1 for further
details about operation.
BR_ADDR [4:0]:
The Burst-ram address number (BR_ADDR [4:0]) indicates the RAM address
to be configured or interrogated. The Burst ram is divided into 2 segments:
the first is Burst Write RAM, which is used to store data to be loaded into the
External SDRAM; the second is the Burst Read RAM, which is used to collect
data read from the External SDRAM. The access to bust-write RAM is always
a write operation while the access to burst-read RAM is always a read
operation. See Figure 24 for the format of the Burst Ram.
• 0x00-0x0F: Burst-Write RAM
• 0x10-0x1F: Burst-Read RAM
BR_BUSY:
The indirect access command bit (BR_BUSY) reports the progress of an
indirect access. BR_BUSY is set high when the register is written to trigger an
indirect access; it will stay high until the access is complete. Once the access
is complete, the BR_BUSY signal is reset. This register should be polled: (1)
to determine when data from an indirect read operation is available in the
SDRAM Indirect Burst RAM Data register or (2) to determine when a new
indirect write operation may commence.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
120
PMC [ PMC-SIERRA, INC ]
