S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
10.1.6 PHY Mapping
In order to support APS and other applications, the RxLink and TxLink blocks have the capability
of remapping the PHY IDs used by the PHY devices over the UL3 or POS-PHY bus to another
PHY ID to be used internal to the S/UNI-ATLAS-3200 and switch. In both the Ingress and
Egress modes, the translation is done on the side of the device facing the PHYs, i.e. in the RxLink
or TxLink block. The RxLink and TxLink use the external address in their calendar, and in
specifying the mapping table. The remainder of the device, including the data queue blocks, use
the translated PHY ID.
To facilitate this function, a table is provided in indirect registers in the RxLink and TxLink
blocks which allows the microprocessor to specify, for any given external PHY address, the
internal PHYID to which the PHY address is to be mapped.
Table 4 PHY Mapping
PHY Device
Address
0
1
2
Indirect Address for
Calendar & Mapping
0
1
2
Data in Mapping Table PHY ID Internal to
ATLAS and Switch
37
12
2
37
12
2
…
…
47
47
7
7
10.1.7 Scalable Data Queue
In all the above configurations, both the input and output interfaces use Scalable Data Queue
blocks (SDQs). There is an Input Data Queue and an Output Data Queue which buffer cells for
the input and output, and a Bypass Data Queue which is used for packet bypass. Each SDQ
offers generic storage and buffering for cells or packets. It has a capacity of 12288 bytes, which
may be carved up into 1 to 48 different FIFOs. The depths of the various FIFOs are highly
configurable (within the bounds set by the total available storage). For example, if a system has
48 STS-1 ATM PHY devices, then one may configure the input and output SDQs to behave as 48
FIFOs (one per PHY), each having 4 cells worth of storage. If there are higher-rate interfaces,
then PHY buffers may be reduced in size or eliminated, to accommodate larger buffers on higher-
rate PHYs. The Input and Bypass Data Queues may be configured to suit the system’s buffering
requirements. However, the Output Data Queue must be set to at least 4 cells for data rates
greater than STS-1, and to at least 12 cells for data rates greater than STS-3. The registers to
configure the Input SDQ are described in Section 11.8, and the registers to configure the Output
SDQ are described in Section 11.11.
Each SDQ maintains a set of per-PHY 11-bit counters of the number of cells or packets currently
in each of the FIFOs, a 32-bit aggregate count of the total number of cells accepted by all the
PHY queues, and a 16-bit count of the total number of cells dropped by all the FIFOs. These
counts are separate from the Cell Processor’s per-PHY counters, and are used for diagnostic
purposes.
Section 13.1 describes how to set up the SDQs.
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Document ID: PMC-1990553, Issue 4
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