S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
11.4 Backward Cell Interface
Register 0x030: Input Backwards Cell Interface Configuration
Bit
31:5
4
3
2
Type
Function
Unused
CALEVEL0
IBCIF_DROP_PRTY
IBCIF_EVEN_PRTY
IBCIF_TxSlave
IBCIFRST
Default
X
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
1
0
CALEVEL0
If CALEVEL0 is logic 1, BI_CLAV is deasserted after the last word of the cell is transferred
into the FIFO. (i.e. the FIFO is full). If CALEVEL0 is logic 0, then BO_CLAV is deasserted
4 words before the end of the last cell that can be accepted, to indicate that the Input BCIF
cannot accept another cell.
IBCIFRST
The IBCIFRST bit is used to reset the 16-cell Input Backwards Cell Interface FIFO. When
IBCIFRST is set to logic zero, the FIFO operates normally. When IBCIFRST is set to logic
one, the FIFO is immediately emptied and ignores reads and writes. The FIFO remains
empty and continues to ignore reads and writes until a logic zero is written to IBCIFRST.
N.B. This FIFO must be reset at startup.
IBCIF_TxSlave
When this bit is a logic 0, then the Input Backwards Cell Interface is an Rx Master interface,
and is configured to interact with another S/UNI-ATLAS-3200 Output Backwards Cell
Interface. When this bit is logic 1, the Input Backwards Cell Interface is a Tx Slave interface,
and is configured to interact with a tester or ASIC.
IBCIF_EVEN_PRTY
When this bit is logic 1, the BI_PAR pin is expected to complete even parity for the
BI_DAT[15:0] bus. When it is logic 0, the BI_PAR pin is expected to complete odd parity for
the BI_DAT[15:0] bus.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
176
PMC [ PMC-SIERRA, INC ]
