S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
11 Normal Mode Register Description
Normal mode registers are used to configure and monitor the operation of the S/UNI-ATLAS-
3200. Normal mode registers (as opposed to test mode registers) are selected when TRS
(UP_ADDR[11]) is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register bits must
be written with logic zero. Reading back unused bits can produce either a logic one or a logic
zero; hence, unused register bits should be masked off by software when read.
2. All configuration bits that can be written into can also be read back. This allows the
processor controlling the S/UNI-ATLAS-3200 to determine the programming state of the
block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise
noted.
4. Writing into read-only normal mode register bit locations does not affect S/UNI-ATLAS-
3200 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell functions that are
unused in this application. To ensure that the S/UNI-ATLAS-3200 operates as intended,
reserved register bits must be written with their default value as indicated by the register bit
description.
11.1 List of Registers
Register 0x000: S/UNI-ATLAS-3200 Master Configuration And Reset..........................151
Register 0x001: S/UNI-ATLAS-3200 Identity / Load Counts..........................................154
Register 0x002: Master Interrupt Status #1....................................................................156
Register 0x003: Master Interrupt Status #2....................................................................162
Register 0x004: Master Interrupt Enable #1 ..................................................................164
Register 0x005: Master Interrupt Enable #2 ..................................................................166
Register 0x006: Master Clock Monitor ...........................................................................167
Register 0x020: Microprocessor Cell Interface Control and Status ...............................169
Register 0x021: Microprocessor Cell Data.....................................................................173
Register 0x022: MCIF Dropped Cells Counter...............................................................175
Register 0x030: Input Backwards Cell Interface Configuration......................................176
Register 0x031: IBCIF Dropped Cells Counter ..............................................................178
Register 0x032: IBCIF Read Cells Counter ...................................................................179
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
144
PMC [ PMC-SIERRA, INC ]
