S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x038: Output Backwards Cell Interface Configuration...................................180
Register 0x039: OBCIF Dropped Cells Counter ............................................................181
Register 0x03A: OBCIF Read Cells Counter .................................................................182
Register 0x040: SYSCLK Delay Locked Loop Register 1..............................................183
Register 0x041: SYSCLK DLL Register 2......................................................................185
Register 0x042: SYSCLK DLL Register 3......................................................................186
Register 0x043: SYSCLK DLL Register 4......................................................................187
Register 0x100: Cell Processor Configuration ...............................................................190
Register 0x101: Cell Processor Routing Configuration..................................................197
Register 0x102: Cell Counting Configuration.................................................................203
Register 0x104: Backward Cell Interface Pacing and Head of Line Blocking................205
Register 0x105: Per-PHY Processing Enable 1.............................................................207
Register 0x106: Per-PHY Processing Enable 2.............................................................209
Register 0x107: AIS/CC Pacing and Head of Line Blocking..........................................211
Register 0x108: Fwd PM Pacing and Head of Line Blocking.........................................213
Register 0x109: Inoperative PHY Declaration Period and Indications...........................215
Register 0x10A: Inoperative PHY Indications ................................................................217
Register 0x10B: Search Engine Configuration...............................................................219
Register 0x10C: SRAM Access Control.........................................................................221
Register 0x10D: SRAM Data LSW (SRAM Data[31:0]) .................................................223
Register 0x10E: SRAM Data MSW (SRAM Data [63:32]) .............................................224
Register 0x110: VC Table Maximum Index ....................................................................225
Register 0x111: VC Table Access Control......................................................................226
Register 0x112: VC Table Write Enable 1 ......................................................................229
Register 0x113: VC Table Write Enable 2 ......................................................................231
Register 0x114: VC Table Data Row 0, Word 0 (LSW) (RAM Data [31:0])....................232
Register 0x115: VC Table Data Row 0, Word 1 (RAM Data [63:32]) .............................233
Register 0x116: VC Table Data Row 0, Word 2 (RAM Data [95:64]) .............................234
Register 0x117: VC Table Data Row 0, Word 3 (MSW) (RAM Data [127:96])...............235
Register 0x118: VC Table Data Row 1, Word 0 (LSW) (RAM Data [31:0])....................236
Register 0x119: VC Table Data Row 1, Word 1 (RAM Data [63:32]) .............................236
Register 0x11A: VC Table Data Row 1, Word 2 (RAM Data [95:64])............................236
Register 0x11B: VC Table Data Row 1, Word 3 (MSW) (RAM Data [127:96])...............236
Register 0x11C: VC Table Data Row 2, Word 0 (LSW) (RAM Data [31:0]) ...................237
Register 0x11D: VC Table Data Row 2, Word 1 (RAM Data [63:32]).............................237
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
145
PMC [ PMC-SIERRA, INC ]
