S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
10.17.4 Writing Cells
The S/UNI-ATLAS-3200 contains a one cell buffer for the assembly of a cell by the
microprocessor for presentation on the Output Cell Interface. Optional header translation and
CRC-10 protection provides full support of diagnostic and OAM requirements.
Cells inserted via the Microprocessor Cell Interface are inserted into the cell stream by the ATM
Layer Cell Processor. The ATM Layer Cell Processor gives an equal priority between cells
received from the Input Cell Interface and cells received from the Microprocessor Cell Interface.
Therefore, it is the responsibility of the management software to ensure that cells are not inserted
via the Microprocessor Cell Interface too frequently (i.e. the management software must ensure
these inserted cells are paced).
Writes are performed through the Microprocessor Cell Interface Control and Status and
Microprocessor Cell Interface Data registers. The steps below outline how to insert a cell through
this interface:
1. Poll the INSRDY register bit of the Microprocessor Cell Interface Control and Status register
until it is a logic 1. Alternatively, service the interrupts that result from setting the INSRDYE
bit in the Master Interrupt Enable register. The INSRDYI bit in the Master Interrupt Status
register is set whenever the INSRDY bit goes high.
2. Write the WRSOC bit in the Microprocessor Cell Interface Control and Status register. At
the same time, ensure that the CRC10, PROC_CELL and PHY[5:0] register bits are set to
their correct values, depending on what operation is required.
If the PROC_CELL register bit is a logic 1, then the cell will be processed in the Cell
Processor as if it came from the Input Cell Interface. If the PROC_CELL register bit is logic
0, then the cell will be passed through without being searched, processed, or counted in any
way, as if it were inserted into the cell stream after the Cell Processor.
PHY[5:0] represents the PHY address that the cell is associated with and will be included in
the search key used for VC identification and used to determine the destination PHY queue.
3. Write the cell contents to the Microprocessor Cell Interface Data register. Each subsequent
write enters the next word in the cell. The words shall be written in the following order, and
all 64 bytes must be written even if some are not used:
Word #
1
2
3
4
5
6
…
16
Contents
1st prepended/postpended d-word
2nd prepended/postpended d-word
ATM Header: GFC, VPI, VCI, PTI, CLP
HEC and UDF fields
1st ATM payload d-word
2nd ATM payload d-word
…
12th ATM payload d-word
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
140
PMC [ PMC-SIERRA, INC ]
