S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Bit
[8:5]
Name
Blocksize[3:0]
Description
The block size of PM cells selects the nominal block of user cells as
follows:
0000
0001
0010
0011
0100
0101
0110
0111
1000
128 cells
256 cells
512 cells
1024 cells
2048 cells
4096 cells
8192 cells
16384 cells
32768 cells
1001-1111 Reserved.
4
3
CLP0_SECBs_Only
When this bit is a logic 1, then SECBs will not be declared due to lost
cells whose CLP = 1. This setting may be used to accommodate
connections on which there is no service guaranteee for CLP = 1 cells.
PM_Rollover_FIFO_E
N
If this bit is logic 0, none of the PM counts will generate entries into the
Count Rollover FIFO.
If this bit is logic 1 then the Performance Monitoring counts will generate
entries into the Count Rollover FIFO.
Counts that are designed to roll over in normal operation (the contents
of rows 0,1, and 2, plus the SECBC counts) do not generate Count
Rollover FIFO entries. A bit in the Cell Processor Configuration
Register (Sat_Fast_PM_Counts) controls whether the four counts that
can increment very quickly (BIP16 errors, and the counts of Lost PM
cells) are excluded from generating Count Rollover FIFO entries.
When a counter is enabled for making entries into the CRO FIFO it will
do so whenever its MSB becomes logic 1, and it will then reset the MSB
to logic 0.
If the Count Rollover FIFO is full, the MSB will remain set until such time
as it can make an entry in the FIFO. The counts continue counting until
they saturate.
2
1
Reserved
Fwd_PM0
This bit is used for internal purposes, and must be programmed to logic
0 at startup, and must not be altered by the microprocessor thereafter,
for proper operation.
If Source_FwdPM is a logic 0, the Fwd_PM0 bit must be set to a logic 1
initially. This bit is cleared upon receiving the first Forward Monitoring
cell, along with the current cell count, BIP-16, and the entire contents of
rows 3 and 4. The Fwd_PM0 bit is used to denote the arrival of the first
Forward Monitoring cell. The Fwd_PM0 bit suppresses accumulation of
the Forward error counts. If this bit is not set, error counts will be
accumulated.
If Source_FwdPM is a logic 1, then if this bit is set to a logic 1 initially,
rows 1 and 7 will be cleared at the end of the first block of user cells.
Initializing Row 0 is the responsibility of the management software
during setup.
0
Bwd_PM0
The Bwd_PM0 bit must be set to a logic 1 initially. This bit is cleared
upon receiving the first Backward Reporting cell. At that time, the
contents of rows 5, 6, and 7 are cleared (except for the Bwd SECBC
count which is copied from the Backward Reporting cell) and Row 2 is
initialized with values copied from the Backward Reporting cell.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
123
PMC [ PMC-SIERRA, INC ]
