S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
The TAT updating process ensures the policing theoretical-arrival-times track the free running
time-of-arrival counter of the ATLAS.-3200 This ensures that connections which have a long gap
between inter-cell arrivals are never mistakenly policed due to a roll over of the free running
time-of-arrival counter.
The CC, RDI and AIS change of state and alarm monitoring process is controlled by the fill status
of the Change of State FIFO. If the change of state FIFO is not used, then this process is not
throttled by the FIFO fill status. If the FIFO is used, then notification of changes of state in CC,
RDI and AIS alarms will be suspended until the FIFO is not full. This ensures the management
software never misses any change of connection status. The Excessive Policing Status bit is also
part of the Change of State FIFO. It is the responsibility of the management software to
ensure the FIFO is read often enough so that the alarm declarations remain compliant with
Bellcore GR-1248-CORE and ITU-T I.610.
Background processes have scheduled processing time available for execution regardless of the
cell data rate.
10.14 Performance Management
10.14.1 Performance Management Flows
The S/UNI-ATLAS-3200 supports a highly configurable internal PM statistics RAM. The VC
Linkage Table is used to index two internal PM RAM locations. Each pointer can access up to
256 unique PM RAM locations. These two pointers can be used to perform simultaneous sinking
and sourcing of a PM flow, simultaneous F4 and F5 PM flows, etc. The PM pointers are located
in the VC Linkage Table in external SRAM, and the fields are as follows:
Table 29 Linkage Table Fields Used in PM
63
0
1 PHYID (6)
2
Reserved
(16)
PM 2
Active
(1)
1
PM 2
Address
(8)
PM 1
Active
(1)
1
PM 1
Address
(8)
VPC
2
VPC
Pointer
Active
(1)
Pointer
(16)
Table 30 PM Activation Fields
Name
Description
PM Active2
PM Active1
PM Addr2[7:0]
Indicates the PM session pointed to by PM Addr2[7:0] is active.
Indicates the PM session pointed to by PM Addr1[7:0] is active.
Indicates which internal PM RAM Address in Bank 2 is to be used for a PM session.
Bank 1 and Bank 2 are completely separate. Many connections may point to the same
PM session; for instance, if an VPC was being split out to its component VCCs, each
VCC table entry, as well as the F4 OAM table entry, might point to a single F4 PM Sink
session. The same strategy would work for the aggregation of VCCs into a VPC.
PM Addr1[7:0]
Indicates which internal PM RAM Address in Bank 1 is to be used for a PM session.
Bank 1 and Bank 2 are completely separate. Many connections may point to the same
PM session; for instance, if an VPC was being split out to its component VCCs, each
VCC table entry, as well as the F4 OAM table entry, might point to a single F4 PM Sink
session. The same strategy would work for the aggregation of VCCs into a VPC.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
118
PMC [ PMC-SIERRA, INC ]
