S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
VP End-to-
End AIS
VP
No cells are generated. The VP End-to-End AIS cell is passed through.
We are assuming that VCs are not switched if the F4 is a Segment End-Point only.
Generate VPC Segment RDI.
Segment
End-Point
only
VP
Segment
AIS
Generate VPC End-to-End AIS cell if APS is not available (and end-to-end VP-AIS
cells are not being received).
VP End-to-
End AIS
VP non-
No cells are generated. The received cells are passed through transparently.
end point
We are asssuming that, if a VP connection is a non-end point, then any VCCs
VP
pointing to that connection are being aggregated into it rather than switched out.
Segment
AIS
This feature is controlled by the F4EAISF5SRDI register bit. When this bit is logic 1, a segment
VC-RDI cell will be generated when an end-to-end VPC-AIS cell is terminated at a VPC end-to-
end point, and an associated VCC segment end-point is switched from that VPC. If this bit is
logic 0, a segment VC-RDI cell will not be generated in this circumstance.
This feature is controlled by the F4EAISF5EAIS register bit. When this bit is logic 1, an end-to-
end VC-AIS cell will be generated when an end-to-end VPC-AIS cell is terminated at a VPC end-
to-end point, and an associated VCC segment end-point is switched from that VPC. If this bit is
logic 0, an end-to-end VC-AIS cell will not be generated in this circumstance.
This feature is controlled by the SegmentFlow bit in the Table OAM Configuration field of the
VC Table. If this bit is logic 1, the VCC is considered to be part of a segment flow, and a
segment VC-AIS cell will be generated when an end-to-end VP-AIS cell is terminated at a VPC
end-to-end point.
This feature is controlled by the F4toF5OAM bit in the OAM Configuration field of the VC
Table. If this bit is logic 1, the F4 to F5 Fault Management scenarios are enabled. If this bit is
logic 0, no F5 Fault Management cells will be generated as a result of the reception of F4 Fault
Management cells. However, the Continuity Check process will still be active on the F4 and F5
levels if the VPC Pointer fields are correctly setup.
This feature is controlled by the F4SAISF5ERDI register bit. When this bit is 1, an end-to-end
VC-RDI cell will be generated when a segment VPC-AIS cell is terminated at a VPC segment
end-point, and the VCC is also an end-to-end point. If this bit is logic 0, an end-to-end VC-RDI
cell will not be generated in this circumstance.
This feature is controlled by the F4SAISF5EAIS register bit. When this bit is logic 1, an end-to-
end VC-AIS cell will be generated when a segment VPC-AIS cell is terminated at a VPC segment
end-point. Note, the VCC connection is not part of a segment flow (SegmentFlow=0). If this bit
is logic 0, an end-to-end VC-AIS cell will not be generated in this circumstance.
This feature is controlled on a per-PHY basis by the APSx register bit (where x is from 0-47).
When the APSx register bit is logic 0, it indicates there is no automatic protection switching on
PHY x . When a VPC connection is configured as a segment end-point only and a segment VPC-
AIS cell is received, an end-to-end VPC-AIS cell is generated immediately, and once per second
(nominally) thereafter. When the APSx register bit is logic 1, an end-to-end VPC-AIS cell is not
generated in this circumstance. No end-to-end AIS will be generated if the connection is already
receiving end-to-end AIS.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
115
PMC [ PMC-SIERRA, INC ]
