S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
It is required that the records of an F5 flow and its enclosing F4 flow be in different banks. The
constituent F5s need not be in the same bank, so long as they are not in the same bank as the F4
connection. If this rule is violated, then all the constituent F5s will be treated as inactive
connections. If the InactiveToUP bit is logic 1 in the Cell Processor Routing Configuration
Register, then cells will be routed to the microprocessor, permitting this condition to be detected
and corrected.
10.13 Background Processes
The S/UNI-ATLAS-3200 performs numerous background processes to perform correct and
compliant OAM-Fault Management cell generation, and alarm monitoring as well as maintaining
the per-connection and per-PHY TAT policing parameters. The background processes are
triggered either by the internally generated 0.5 second clock event, or by the external 0.5 second
clock input pin.
Each Cell Processor maintains 4 background processes. They are:
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RDI cell generation.
AIS/CC cell generation.
TAT updating.
CC, RDI and AIS Change of State and alarm monitoring.
The VC Table Maximum Index register controls the maximum 17-bit VC Table address which
must be monitored by the various background processes.
The RDI cell generation process is controlled by the status of the Backward Cell Interface to
which the process must send generated RDI cells. If this FIFO is filled, no RDI cells will be
generated, and the RDI background process will pause until room becomes available. This
ensures that no RDI cells will be lost due to overflow of the Backward Cell Interface.
The AIS/CC cell generation process is controlled by the status of the Output Cell Interface, and
by a programmable threshold that determines the maximum rate at which AIS/CC cells can be
generated. If an AIS or CC cell is generated, the process will be suspended until the expiry of a
user programmable counter threshold. However, AIS cells will only be generated on PHYs that
have room in the Output Cell Interface to take them. Connections which, after a timeout period,
still cannot insert an AIS cell due to a full Output Cell Interface queue will be skipped, to ensure
that other connections are not denied the ability to send AIS cells. If a PHY has cells destined for
it, but its Output Cell Interface FIFO is full, and the PHY does not accept any cells whatsoever
for a programmable number of cell periods (the Inoperative PHY Declaration Period register,
which defaults to 256 cell periods) then the PHY will be declared inoperative, an optional
interrupt will be asserted, and any subsequent generated cells destined for that PHY (CC, AIS,
RDI, Loopback, Bwd PM and Fwd PM) will be immediately discarded to prevent them from
slowing the generation of cells to the remaining PHYs. The PHY queue will be declared
operative again as soon as it accepts a single cell from S/UNI-ATLAS-3200.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
117
PMC [ PMC-SIERRA, INC ]
