RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81140: Receive Status FIFO Enable Register (RSTAT_EN_REG)
Bit
Type
Function
Default
15:6
5
RO
R/W
R/W
R/W
R/W
R/W
R/W
Unused
X
0
0
0
0
0
0
R_LINE_RESYNC_EN
T_LINE_RESYNC_EN
4
3
BITMASK_CHANGE_EN
EXIT_UNDERRUN_EN
ENTER_UNDERRUN_EN
RECEIVE_QUEUE_ERR_EN
2
1
0
The above enable bits control the corresponding status bits in the
RCV_STAT_FIFO. When an enable bit is set to a logic 1, the corresponding
receive status event will cause an entry to be made into the RCV_STAT_FIFO.
This mask applies to all receive queues.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
272
PMC [ PMC-SIERRA, INC ]
