RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81100: Master Interrupt Enable Register (MSTR_INTR_EN_REG)
Bit
Type
Function
Default
15
14
13
12
11
10
9
RO
RO
Unused
Unused
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
R_UTOP_RUNT_CL_EN
UTOP_LFIFO_FULL_EN
T_UTOP_XFR_ERR_EN
T_UTOP_FULL_EN
UTOP_PAR_ERR_EN
Reserved
8
7
6
5
4
RAM_PAR_ERR_EN
Reserved
3
2
Reserved
1
Reserved
0
A1SP0_INTR_EN
The above enable bits control the corresponding interrupt bits in the
MSTR_INTR_REG. When an enable bit is set to a logic 1, the corresponding
error event will cause INTB to go active.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
270
PMC [ PMC-SIERRA, INC ]
