RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81110: A1SP Interrupt Enable Register (A1SP_EN_REG)
Bit
Type
Function
Default
15
14
13
12
11
10
9
RO
RO
Unused
Unused
X
X
X
X
X
X
X
X
X
0
RO
Unused
RO
Unused
RO
Unused
RO
Unused
RO
Unused
8
RO
Unused
7
RO
Unused
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TALP_FIFO_FULL
RSTAT_FIFO_FULL
RSTAT_FIFO_EMPB
TIDLE_FIFO_FULL
TIDLE_FIFO_EMPB
OAM_INTR
5
0
4
0
3
0
2
0
1
0
0
FR_ADV_FIFO_FULL
0
The above enable bits control the corresponding interrupt bits in the
A1SP_INTR_REG. When an enable bit is set to a logic 1, the corresponding
error event will cause the A1SP_INTR bit to be set in the MSTR_INTR_REG.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
271
PMC [ PMC-SIERRA, INC ]
